Intel X86 architecture is full already 20 years,ugg outlet online, compared with 486, Pentium is a big step forward, and P II ahead of the pace is not so big, X86 CPU development appears to have an end.Intel is very clear, is the X86 instruction set limit CPU to improve their performance, therefore, they are the same hp work together to develop the next generation of instruction set architecture (Instruction Set Architecture, ISA): EPIC (Explicitly Parallel Instruction Computing, explicitly parallel instruction computing).
For Intel, IA64 (Intel 64 Architecture) is the next 10 to 15 years of architecture.The new ISA will make Intel from X86 architectural constraints, thus design beyond all existing RISC CPU and X86 CPU new processor.
Then the EPIC advanced in what place?Why Intel would make it become the chip giant X86 architecture?One, IA32 problem we know, engineers can improve each clock instruction execution to improve performance,Coach Outlet Store Online, Intel's new instruction set is to give instructions, decode easily, easier to execute in parallel.
This can not be limited to the development of new type processor.However, for engineers, compatible with 8086 X86 instruction set is always necessary to complete a task.After all, compatible before acting product is that Intel grow up with key factors, but also can protect the user's original investment and use of millions of application software.
If so, why give up the whole of X86 instruction set to start again?The lack of X86 in what place?(1) variable instruction length X86 instruction length is uncertain, and there are several different formats, resulting in X86 CPU decoding is very complicated, in order to improve the working frequency of CPU, extended CPU in the pipeline, and long lines in the branch prediction error situations, it will bring about CPU stagnation time longer malpractice.
(2) the lack of X86 register instruction set architecture only 8 general registers, and actual use only 6.This situation with modern superscalar CPU extremely incommensurate, although the engineers with register renaming techniques to compensate for this shortcoming, but resulted in CPU are too complex, too long in the situation of pipeline.
(3) the memory access instructions X86 can be accessed for the memory address, and modern RISC CPU use the LOAD / STORE mode, only the LOAD and STORE instructions can be read from the memory data register, all other instructions only to register in operand calculation.
In the current CPU is the speed of memory speed 5 times or 5 times more cases, after a working model is the right path.(4) floating point stack X87 FPU is by far the most slow FPU, one of the main reasons is that the X87 instruction using an operand stack.
If there is not enough registers to calculate, you have to use a stack to store data, it will waste a lot of time to use the FXCH command (i.e. the correct data to the top of the stack).(5) the 4GB limit this does not appear to be a problem, but, in 6 years ago, the mainstream PC only the 4MB memory, and now most of PC equipped with 64MB memory above,Christian Louboutin Sale, is 16 times larger than before, therefore, in the next ten years, PC memory 1GB break never surprising, but the current large scale the server has used the 1GB memory above 4GB, break through the memory will come soon.
(6) chip in all used to enhance the X86 performance of CPU method, such as register renaming, huge buffer, out-of-order execution,Beats by Dre Studio Michael Jack, branch prediction, X86 instruction transformation and so on, all make CPU chip area becomes larger, also restricted the working frequency increases further,Coach Outlet, and additional integration of these transistors are only to solve the the X86 instruction problem.
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